The present invention relates to the field of integrated circuits, and more specifically to techniques to effectively provide greater number of external pins for input and output of data.
Semiconductor technology continues to improve. This technology allows greater and greater functionality to be provided by a single integrated circuit or "chip." Signals are input to and output from the chip using external pins or pads. The chip interfaces to external circuitry, possibly on other chips, using the external pins.
The performance of a system depends in part on the amount or rate at which data can be transferred on and off the chip. This transfer rate may be referred to as the data bandwidth. One technique for increasing system performance is to provide more rapid transfer rates. This may be accomplished by improvements in process technology or circuit design. Another technique to increase system performance is to transfer a greater amount of data at one time (or "in parallel"). Therefore, for greater performance, it is important there are many external pins available for input and output of user data.
In an integrated circuit, certain pins are sometimes dedicated to functions other than user data I/O. For example, in a programmable integrated circuit or device such as a PLD or FPGA, some pins may be dedicated to the programming and testing (such as JTAG boundary scan testing) of the device. These dedicated external pin reduce the number of pins available for user I/O. The performance of the chip may be detrimentally affected since not as many user I/O signals may be transferred in parallel. Other programmable devices may include integrated circuits such as microprocessors, coprocessors, microcontrollers, programmable controllers or sequencers, graphics controllers, memories, DRAMs, SRAMs, EPROMs, serial EPROMs, Flash memories, and many others.
Consequently, there is a need for techniques of effectively providing greater number of external pins for input and output to obtain higher performance. Specifically, there is a need for techniques to reduce the number of external pins dedicated to functions other than user I/O, which would make greater number of external pins available for the input and output of user data.